1. Field of the Invention
This invention relates to a method of fabricating microcircuit devices commonly used in home and office computers, and more particularly, has to do with a method for producing multiple level conductor material patterns in co-parallel or stacked parallel planes, embedded in insulator material, and having a constant and uniform separation between pattern levels in a manner highly advantageous for bubble memory circuit devices.
2. Description of the Prior Art
Microelectronic devices such as hybrid circuits, silicon integrated circuits, and magnetic bubble domain circuits are known in the art. These devices typically comprise components mounted on or fabricated in a substrate which is processed to provide the required circuit conductor interconnections for single-layer or multi-layer conductor patterns. Conductor patterns are typically made of aluminum copper alloy or gold. In bubble domain circuits, layers of different conductor materials such as a first level layer of aluminum copper alloy and a second layer of permalloy (nickel iron alloy) are formed on a suitable substrate, such as garnet.
Conventional bubble domain circuit devices have multi-layer, multi-level conductor patterns spaced by an insulator layer covering the first level of conductor material pattern, atop the substrate of garnet. Because of the way these devices have previously been manufactured, the insulator layer varies in its spacing from the garnet substrate depending on whether the insulator area is over or between portions of the conductor material pattern. The next conductor pattern level, e.g. nickel iron alloy is applied to the insulator layer to form the bubble memory device. Variations in insulator layer spacing relative to the garnet thus are carried over to the nickel iron alloy second level pattern, and nonuniform spacing results between regions of the nickel iron alloy second level pattern and the garnet substrate.
Nonuniform spacing between the nickel iron alloy or other second level pattern and a garnet substrate, adversely affects bubble memory device performance. And, as bubble domains are scaled down in size to 2 .mu.m or even smaller, poor device performance traceable to spacing disuniformities becomes particularly significant and will result in reduced yield of good devices in production.
In addition to these problems, layers of conductor or insulator material that contour or cross-over are subject to cracking, thinning, narrowing, and developing discontinuities at corners of the contour transition.
A further problem of significance in manufacturing multi-layer, multi-level conductor patterns is that the presence of appreciable contour in resist patterns makes difficult the obtaining of clear and distinct photo exposures, which in turn limits the obtainable minimum in line widths, the number of interconnections per unit area, and the maximum number of layers that can be achieved.
Among publications in the field is U.S. Pat. No. 3,985,597 to L. Zielinski, issued Oct. 12, 1976, which discloses a method for forming conductors embedded in dielectric to form a planar surface. See also the process disclosed in IBM Technical Disclosure Bulletin, Vol. 17, No. 12, July 1974, at page 352, copies of which are being furnished with this application.